1. Field Of The Invention
This invention relates to flash EEPROM (electricallyerasable programmable read only) memories and, more particularly, to apparatus for causing a flash EEPROM memory to generate a signal indicating the status of an internally controlled operation.
2. History Of The Prior Art
Recently, a new type of electrically erasable programmable read only memory called flash EEPROM has been devised. Such a memory array is disclosed in U.S. patent application Ser. No. 667,905, entitled LOW VOLTAGE EEPROM CELL, Lai et al, filed Nov. 2, 1984, and assigned to the assignee of the present invention. Flash EEPROM may be electrically erased and reprogrammed without removing the memory from the system. Flash EEPROM memory arrays are popular because they are a relatively inexpensive way to provide large memory arrays which may be reprogrammed without removing them from a system with which they are used. Flash EEPROM is available in memory arrays up to two megabits.
A difficulty with flash EEPROM, however, is that erasure is accomplished by applying a high voltage to the source terminals of all of the transistors (cells) used in the memory. Because these source terminals are all connected by metallic busing in the array, the entire array is erased and must be reprogrammed. Thus, the reprogramming effort required for flash EEPROM is very extensive.
Because of this, with large arrays there are a great number of chances for one programming flash EEPROM to inadvertently provide incorrect commands to the chip. Although some of these incorrect commands may have no effect on the operation of the circuitry, others may have a very deleterious effect. Initial efforts with flash EEPROM have disclosed that the programming of such circuitry is so complicated that it is desirable to limit the ability of a programmer to provide inadvertent commands which may adversely affect the flash EEPROM.
To overcome this problem, an arrangement has been devised by which circuitry called command interface circuitry is interposed between the programmer and the flash EEPROM circuitry U.S. patent application Ser. No. 665,643, entitled COMMAND STATE MACHINE, M. Fandrich et al, filed Feb. 11, 1991, and assigned to the assignee of the present invention discloses such an arrangement. The arrangement controls the transfer of signals to and from the flash EEPROM and eliminates the ability of the programmer to provide signal combinations which might be able to affect the circuitry of the memory array in an undesirable manner. Essentially, the invention eliminates the possibility of generating unwanted, undesirable, and unknown combinations of signals which might somehow create a defect in the operation of the memory array.
The command state machine and its associated circuitry receive the commands from a programmer and accomplish the various allowed results. The command state machine controls a write state machine which accomplishes both write operations and erase operations. The time required for each of these operations is significantly longer than is the time required for writing or erasing conventional memory. For example, a write to the flash EEPROM may require approximately ten microseconds rather than the typical 120 nanoseconds required for writing to more conventional memory. An erase operation typically requires up to onehalf a second to accomplish.
Even though these times are long, there are still many situations in which it is desirable to write to and erase flash EEPROM during the operation of the computer system of which it is a part. If the other circuitry in the computer system must wait for a write to or the erasure of the flash memory, the system delay will be very extensive. For example, if a central processor initiates a write operation by the command state machine controlling the programming of a flash memory array and then must wait for the result of that operation before it can proceed, the delay to the system is inordinate compared to a typical computer wait period. It is, therefore, desirable that such delays be obviated in some manner.